NUIBlaze – embedded debugging

Abstract

Main part of modern architectures of processors, microcontrollers, signal processors (DSP) and other VLSI chips is defined using narrow specialized “programming” languages like VLSI Hardware Description Language (VHDL), Verilog or AHDL[3]. Sometimes developing companies like ARM or Xilinx release very simple versions of their products with full source code for educational purposes[1]. It is good opportunity to learn theoretical issues of work and developing chips like DSP, to analyze example structures or simulate its work. Software simulation is acceptable for relatively incomplicated modules, but when becomes to test more advanced and complex modules simulation is time consuming and insufficient. Quite new possibilities in this area opens when becomes to use In System Debuggers (ISD). With ISD it is possible to make tests of embedded systems, even running ones, without necessity to stop them at all. Unfortunately price to pay for cheap or even free training releases of microcontrollers, DSP processors, etc. is lack of this kind of interface inside. Example of simple realization of ISD is NUIBlaze
Authors: Krzysztof Kępa, Krzysztof Rutecki, dr Fearghal Morgan

1. GENERAL DESCRIPTION

Architecture of NUIBlaze is based on simple core of PicoBlaze microcontroller [1]. NUIBlaze ISD includes: full UART serial interface and set of sixteen 8-bit general purpose registers, which can be mapped as working registers into bigger project, like signal processor (DSP). Software controlling work of NUIBlaze gives possibility to read and modify every particular GP register in set using serial interface. If one of these registers is mapped as resource of DSP (i.e. work register) it gives a possibility of continuous watching and modifying of data in working (not being simulated) system. In this way has been developed a flexible, easy to implement in various systems and well documented (including source code) In System Debugger.



For outside world NUIGBlaze is visible just like ordinary RS-232C terminal - DCE device. It has complete implementation of RS232 port, with CTS, DSR, RTS control lines. From programming point of view all these lines, including as well Tx and Rx lines are visible as bits in Status Register (respectively 7th, 6th, 3rd bit in Status register) or dedicated register (Tx and Rx registers) in PicoBlaze I/O space. All of them are controlled from software level.

I/O space is implemented as a virtual memory area with access achieved by IN, OUT assembler instructions. In fact every block mapped into this space is connected by tri-state buffers to common unidirectional buses (PORT_IN, PORT_OUT) and mapped under desired memory address. Exclusive access of connected blocks to common data bus is achieved by using additional bus (PORT_ADDRESS) which select one active block. Other unselected blocks, change their output to Hi-Z to avoid collisions of data. Access to block from code is provided by specifying source/target memory address in IN, OUT instructions. In architecture section we may see declaration of used external components, like PicoBlaze and UART modules provided by Xilinx. It was necessary to implement additional registers mapped to PicoBlaze I/O space to control issues like: speed of serial transmission, state of UART FIFO buffers, interrupt sources.