NUIBlaze – embedded debugging cd.

2. HARDWARE

architecture Behavioral of NUIBlaze is
PicoBlaze with ROM code (2.1)
UART (2.2)
interrupt resolution function (2.3)
begin
General Purpose, Configuration registers (2.4)
Address decoder (2.5)
end Behavioral;
PicoBlaze core

The Constant (k) Coded Programmable State Machine (KCPSM) Pico Blaze is a fully embedded 8-bit microcontroller macro provided by Xilinx without any License fees. It has been developed with one dominant factor being held above all others–its size. The result is a microcontroller that occupies just 76 Spartan-IIE slices. Together with this small amount of logic, a single block RAM is used to form a ROM store for a program of up to 256 instructions. Even with such size constraints, the performance is respectable at approximately 40 MIPS, depending on device speed grade. The PicoBlaze module is totally embedded into the device and requires no external support. Any logic can be connected to the module to provide ultimate flexibility [1].



UART

The macros provide the functionality of a simple UART transmitter and receiver, each with fixed characteristics of: 1 start bit, 8 data bits(LSB first), no parity,1 stop bit.



Although standard baud rates from 9600 can be supported these macros are also capable of baud rates exceeding 10 M-bit/second offering an easy way to communicate between Xilinx devices[2].

To establish connection at desired speed, it is necessary to define and put into Baud Rate Register (BRR) clock division factor used in UART internal clock. It can be made according to following formula[2]:

As well as being able to use these macros as a pair to communicate each other, they are also fully compatible with standard UART communication such as to a PC.


INTERRUPT RESOLUTION

Using core of PicoBlaze gives user an opportunity to use interrupts and to write pseudo event-driven code. The main problem of only one INT line in Pico is available can be easily resolved by using Interrupt Trigger function. This function checks if any of enabled in special Interrupt Mask Register sources wants to report an interrupt. If yes and particular source is enabled then function triggers off microcontroller Interrupt Service Routine (ISR). Detection of source of interrupt can be made by checking bits in Status and Interrupt Register, this procedure is left to implement in ISR section.

function check_int(int_src, int_mask : in std_logic_vector) return std_logic is variable trig_irq : std_logic := '0';
begin
for i in int_src'reverse_range loop
if (int_src(i) and int_mask(i))='1' then trig_irq:='1'; end if;
end loop;
return trig_irq;
end;

GENERAL PURPOSE and CONFIGURATION REGISTERS

General Purpose Registers (GPR) is a block of 16 independent, 8-bit synchronous registers mapped into PicoBlaze I/O space (starting from GPRegAddress). Any of them can be freely mapped as standalone or in group up to 16 as an internal work registers set used by i.e. DSP or other microcontroller. Data stored in these registers can be viewed and changed directly using any PC with terminal emulator and simple syntax presented in next chapter.





Bits in SR indicate state of serial FIFO buffer and the rest of a full RS232C interface lines (RTS,CTS, DSR). Bits on approviate positions in IR indicate which events from SR can trigger off an interrupt. It means that if bit in IR is asserted then corresponding bit from SR can be source of interrupt.

ADDRESS DECODER

Address decoder is necessary to activate only one from set of register connected to common IN and OUT buses. All other registers are forced to change their output to Hi-Z state what is necessary to avoid data clashes (wired AND) during Read operation and changing data in all registers during Write.